Appendix Six

Appendix Six: Case Study of Technical Specification

Objective:

To provide an example of an actual detailed ASIC specification.

An ASIC specification should create an unambiguous description of an ASIC device that guides the ASIC designer's development work, the ASIC vendor's manufacturing, test and screening work, and the system implementor's work. With this description, which may exist at many levels, the manager of an ASIC program can measure the technical progress of the ASIC design and provide support for contracting and procuring the ASIC parts. In this appendix, we examine a case study of a technical specification. Please see the "ASIC Design" section: Chapter 1 for a description of a generic technical specification of an ASIC.

Along with conventional paper-based documentation, modern ASIC design produces a significant amount of computer-based information. This may include a high-level language behavioral description, a gate-level circuit net list, files of test patterns, schematic images, etc. No ASIC specification is complete without a comprehensive listing and configuration management of these files and their various revisions.

Based around an actual part specification, we intend this appendix not to deliver a "fill-in-the-blanks" template but to show all major areas requiring technical specification. Studying this appendix will provide you with the kind of information essential to support the activities discussed in the first paragraph above. The example ASIC we chose comes from the NASA Cassini spacecraft.

The spacecraft's mission is to orbit the planet Saturn in the late 1990s and gather scientific data. Upon arrival in the Saturn system, the spacecraft will launch a probe to the Saturnian moon, Triton, where, among other experiments, it will explore Triton's unusual carbon chemistry.

The ASIC itself is known as the Attitude and Articulation Control Subsystem Remote Terminal Input/Output Unit or IOU, for short. As part of the control and data interface, the IOU supports the spacecraft subsystem responsible for steering and dynamic configuration control.

The following are actual pages from a specification. We have added brief comments. The comments are separated from the pages by horizontal divisions such as the one below.

This first page below shows the IOU gate array table of contents. The following gives a brief introduction to each major section of the technical specification.

                    TABLE OF CONTENTS
Scope....................................................5
Applicable Documents.....................................5
Conventions Used.........................................5
Additional Requirements..................................6
1.  Chip Overview........................................7
2.  IOU ASIC Signal Designations and Descriptions........11
3.  Functional Description...............................14
  3.1 IOU Gate Array Timing Chain........................15
  3.2 IOU Gate Array Address Decoder.....................15
  3.3 IOU Gate Array Memory Control......................15
  3.4 IOU Gate Array Manchester Encoder/Decoder..........16
  3.5 IOU Gate Array Bus Select & AACS Bus I/F...........16
  3.6 IOU Gate Array User I/F............................16
  3.7 IOU Gate Array Discrete I/O........................17
  3.8 Worst case timing specifications and diagrams......18
4.  Testability Constructs...............................30
  4.1  Use of Scan.......................................30
  4.2  NAND tree for DC tests............................30
5.  Electrical Characteristics...........................31
  5.1  Electrical Test Requirements......................31
  5.2  Absolute Maximum Ratings..........................32
  5.3  Recommended Operating Conditions..................33
  5.4  DC Characteristics................................34
    5.4.1  DC Electrical Performance Characteristics.....34
    5.4.2  I_DDQ Testing..................................36
    5.4.3  Pulldown Resistors............................36
    5.4.4  Pullup Resistors..............................36
  5.5  AC Characteristics................................37
    5.5.1  AC Electrical Performance Characteristics.....37
    5.5.2  Timing Analysis...............................38
      5.5.2.1  Pre-Layout Timing Margins.................38
      5.5.2.2  Post-Layout Timing Margins................38
      5.5.2.3  Tester Specification Limits...............38
    5.5.3  Tester Load Circuit...........................39
  5.6  Burn-In...........................................40
    5.6.1  Static Burn-In................................40
    5.6.2  Dynamic Burn-In...............................40
    5.6.3  Burn-In Configuration.........................41
    5.6.4  Delta Limits..................................43
6.  Physical Characteristics.............................44
  6.1  Pin Assignment....................................44
  6.2  Bonding Diagram...................................45
  6.3  Package Outline...................................47
  6.4  Marking Diagram...................................48
7.  Device Statistics....................................49
8.  Exceptions to CS515577B..............................50

This list of tables and figures gives a quick look at the design technical content of the spec.

LIST OF TABLES

Table 2-1.  Signal Description...............................12
Table 3-1.  IOU Memory Map...................................15
Table 3-2.  IOU GA Worst Case Timing Spec....................18
Table 5-1.  Electrical Test Requirements.....................31
Table 5-2.  Absolute Maximum Ratings.........................32
Table 5-3.  Recommended Operating Conditions.................33
Table 5-4.  DC Performance Characteristics...................34
Table 5-5.  AC Performance Characteristics...................37
Table 5-6.  Burn-In Connections..............................41
Table 5-7.  Delta Limits.....................................43
Table 6-1.  Connections Table................................46

LIST OF FIGURES

Figure 1-1.  IOU GA in RT Input/Output AACS..................8
Figure 1-2.  IOU GA Block Diagram............................9
Figure 1-3.  IOU GA Module Diagram...........................10
Figure 2-1.  IOU GA ASIC Symbol..............................11
Figure 3-1.  AACS RT IOU/USER IF Timing......................19
Figure 3-2.  Status Read Cycle...............................20
Figure 3-3.  Local Echo Enable Write Cycle...................20
Figure 3-4.  USERIF Write Cycle..............................21
Figure 3-5.  USERIF Read Cycle...............................22
Figure 3-6.  SRAM Write Cycle................................23
Figure 3-7.  SRAM Read Cycle.................................24
Figure 3-8.  PROM Read Cycle.................................25
Figure 3-9.  Zero Crossing Deviation +150 on Manchester......26
Figure 3-10. Status Word Read - Valid Word Manchester........27
Figure 3-11. Zero Crossing Deviation -150 on Word Manchester.28
Figure 3-12. Status Word Read - Valid Word Manchester........29
Figure 5-1.  Switching Test Circuit and Waveforms............39
Figure 6-1.  IOU GA Pinout Assignments.......................44
Figure 6-2.  Bonding Diagrams................................45
Figure 6-3.  Package Outline (84 pin Flatpack)...............47
Figure 6-4.  Marking Diagram.................................48

Scope

The "Scope" section of the technical specification provides a clear definition of the document, including what the specification covers and how to use it.

Applicable Documents

The list of "Applicable Document," together with this technical specification, contain all requirements levied on the ASIC.

Conventions

"Conventions" covers any special notation used in the technical specification.

Scope

This document is a procurement specification for IOU Gate Array devices. It represents the functional specifications for the IOU Gate Array along with its electrical characteristics, physical characteristics, device level statistics and physical characteristics.

This document shall be the sole source of design and procurement specifications for the IOU Gate Array, and shall supersede any other specification documents issued prior to this release.

Applicable Documents

General Specifications for Microcircuits, 13 May 1991, The Cassini ASIC Boilerplate Spec, Rev. C
This document establishes the general design system, manufacturing and testing requirements for the Cassini Gate Array Application Specific Integrated Circuit (ASIC) parts.
Any applicable exceptions to the Cassini ASICs Boilerplate Spec, Rev. C can be found in Sec. 9 of this ST drawing.
MIL-M-38510J, Microcircuits, General Specification for,
MIL_STD-883D, Test methods and Procedures for Microelectronics
C/C AACS functional specifications
AFC functional specifications
RT Input/Output Unit AACS Cassini Mission Hardware Design Requirements (JPL D-10081)
The Gate Array Design Manual from The Vendor, July 1991
Primary sources of functional and environmental requirements for this device:
RTIOU (Remote Terminal IOU) Attitude and Articulation Control Subsystem Cassini Mission H/W Requirements

Conventions Used

All signals are active high unless designated with a "B": after a signal name. For example, "ALE" is active high and "WRB" is active low.

Additional Requirements

"Additional Requirements" supplement other requirements the ASIC vendor must meet. In the example ASIC, additional requirements calls for the vendor to perform activities a, b, and c, on the ASIC design, using the vendor's tools at the vendor site. Some of this information is to be given back to JPL for further analysis.

Additional requirements d and e have to do with JPL requirements for appropriate types of information format and tools.

a. Functional Delay Simulation: To be derived from each final application specific electrical design and electrical design and layout (i.e. post-routed design). Simulation shall be accomplished by using actual delays as computed from the placement and layout of the device as it will be fabricated. Actual delays shall include the contribution associated with the delay through the gate as well as the contribution due to actual metal capacitance and loading on the output(s). Using these actual delays, the application specific design shall insure the absence of timing violations in the circuit. Such timing violations shall include, but not limited to, setup, hold, critical delay path, and circuit race conditions due to variations in process, temperature, supply voltage and radiation. The simulated circuit behavior at the two (fast and slow) worst case extremes of temperature, supply voltage and process shall be identical states at the specified strobe time (usually at the end of a typical strobe cycle where all signals are stable).

b. Layout Verification: Mask level design rule checks, electrical rule checks, and connectivity checks for each application specific design shall be accomplished. Rule checking will encompass the following rules set:

b1. Design layout rules as a manufacturer's controlled document. (The Vendor Document Control Number 43606 -- Specification for Design Rules, 1.5-micron CMOS Twin-Tub SC/AGA Process)
b2. A list of the macros in the manufacturer's macrocell library, macro cell performance data and macro cell simulation verification data. Performance data shall be guaarenteed for all hard macrocells. Soft macrocells in The Vendor Library will provide some estimated performance numbers which may vary with each layout.
b3. Software packages designed by the manufacturer in the gate array design process.
b4. Design rule check (DRC) and electrical rule check (ERC) software verification. The manufacturer's DRC and ERC software shall be run on a design which contains known rule violations' the output shall be presented and must show that violations were flagged.
b5. Layout versus schematic (LVS) checker. Manufacturer must demonstrate the effectiveness of the LVS software.
b6. Fault simulators used for fault grading is "VERIFAULT".

The manufacturer will explain any rules not checked and all error reports produced by the checker. The LVS check will ensure that the layout matches exactly the logic schematic simulated by the application specific integrated circuit (ASIC) designer.

c. Power Routing Simulation: Derived from each application specific electrical design and layout. The worst case simulation of power buses shall show that at no time shall the localized bus current density exceed specification for bus current density of power bus material as defined in the Cassini ASIC Boilerplate Spec (rev. C). Power routing simulation must be based upon the actual placement of cells within the array.

d. Test Vectors: The vectors shall be supplied on a magnetic tape and shall be identified by test tape number and revision letter.

e. The JPL contract technical manager will approved the fault simulator.

1. CHIP OVERVIEW

These two documents contain information about the IOU ASIC's system I/O and its overall function. We have provided some detail to support the application of the device, much as an off-the-shelf device data book supports functional discussion. The IOU gate array specification shows how the IOU gate array fits into the RT-IOU system and the gate array block diagram respectively.

IOU gate aray implements the following functions:

Provides the "glue logic" for the micro by generating address decoding and and control signals for reading PROM and accessing SRAM.
Conditions the 12 MHz oscillator output to provide a 4 MHz clock for the 80C85 microprocessor.
Acts as a micro I/O peripheral with two "ports." One of these ports is via a Manchester Encoder/decoder interface to the AACS Bus in the upper right of Figure 1.1. The second port is the "user interface," a set of signals that interface to the "User Electronics" shown in the lower right of Figure 1.1.
Provides two functins related to "time management." The first such function is a free-running 16-bit event timer that shall be incremented every 0.1 ms, and shall therefore roll over every 6.5536 seconds. The 80C85 shall be able to cause the state of the timer to be captured at any time without disturbing the cound, and therefore read out the counter value. The second such function shall be a free- running timer that gerneates an interrupt to the 80C85 every 0.5 ms.

Summary of major features:

Manchester II encoder/decoder
Generation of IOU clocks
Generation of memory mapped decodes for IOU control
to accept memory decodes, generate PROM and SRAM control signals
Selects AACS BUS A or B and provides interface to the AACS bus.
Provides USER interface
General purpose signals are provided (2 discrete in and 2 discrete out)

The block diagram in Figure 1.1 shows how the IOU gate array fits into the "Remote Terminal Input Output Unit Attitude & Articulation Control Subsystem." It highlights its interfaces to the other components of RT-IOU-AACS. Figure 1.2 shows a block diagram of the IOU gate array. All of the blocks implemented by IOU gate array will be discussed in Chapter 3.

CHIP OVERVIEW

(CONTINUED)
These two diagrams are the internal and external functional-block- level structures related to the IOU ASIC. They give a quick look at the ASIC's function and logical I/O structure.

Fig. 1.1 IOU GA as a block of the RT-IOU AACS

Fig. 1.2 IOU GA Block Diagram

2. IOU SYMBOL

This is the symbol for the IOU gate array. It has many uses in CAD- supported design development and simulation. It also provides a quick look at the signal I/O for the ASIC, show the signal names and their active state (the circles on the control I/O signals indicate that they are active low), and the signal direction (I, O, or I/O.)

IOU gate array diagram

Signal Table

This table lists the IOU Gate Array signals and their descriptions. Actual pin assignments are specified in section 6. Pad locations on the die are assigned in conjunction with the Vendor during the layout phase in order to conform to the pin assignments and bonding rules.

There are a total of 76 signal pins which includes "Master reset, scan signals and parametric NAND tree signals." The ASIC uses an 84-pin ceramic flatpack with four power pins and four ground pins.

IOU Gate Array signal table

3. FUNCTIONAL DESCRIPTION

This section describes various functional blocks of an ASIC. The functional description should be written with a user of this ASIC in mind. It should describe features of each functional block, various modes of operations, different registers it may contain, etc. All modes of operations should be described with timing diagrams. All acronyms used in the specification should be defined.

This section begins with a definition of terms and acronyms shown below.

Use the following defintions for a quick reference.

DEFINITIONS

AACSE		AACS corntrol Electronics
A/B		AACS Bus Select
BC IOU	Bus Controller Input Output Unit
C/C		CRAF/Cassini
EFC		Engineering Flight Computer
F.E.		Falling Edge
GA		Gate Array
ISB		Inter Subassembly Bus
I/F		Interface Face
RT IOU	Remote Terminal Input Output Unit
R.E.		Rising Edge
T/R		Transmit/Receive
F/W		Firmware

Note: In this document, unless otherwise specified, IOU => Both BC and RT IOU.

FUNCTIONAL DESCRIPTION

(continued)

In this example, sections 3.1 to 3.7 of the specification describe the functional modules of the IOU gate array. Table 3-1 represents an IOU Memory Map, which is important information as an IOU user can use it to understand the allocation of the memory space. As a designer you want to describe the ASIC design explicitly, accurately, and in as much detail as possible. Use the specification of any standard VLSI component as a guide to write the details about the ASIC's functional description. Section 3.8 of the example specification lists the important IOU gate array worst-case timing specification from the user's viewpoint. These numbers reflect the results of extreme conditions such as worst-case condition at minimum voltage, high temperature, worst-case process and best-case condition at maximum voltage, low-temperature, and best-case process variations. The numbers in Table 3-2 do not reflect any guard bands from the point of view of a tester. The special section on AC characteristics also reflects the minimum and maximum AC parameters that a vendor has to guarantee in a manufactured device and those numbers reflect the vendor's tester guard bands.

3.1 IOU Gate Array Timing Chain:

Function:
- Generates IOU Clocks
Divide down oscillator 12 MHz square wave input to generate:
- C4MHZ (4 MHz Square Wave)
- C1MHZ (1 MHz Square Wave)
- T15MS (200 MHz 80C85 Interrupt)

3.2 IOU Gate Array Address Decoder:

Function
- Generate memory mapped decodes for IOU control
- 80C85 has 16 bit address
- IOU Memory map

TABLE 3-1 IOU MEMORY MAP

3.3 IOU Gate Array Memory

Accept Memory Decodes, Generate PROM and SRAM control signals
PROM 1,2
- Read control - "PROMOEB", "PROMTEB" - Enable read
SRAM
- Enable Read - "SRAMOEB"
- Enable Write - "SRAMWEB"
Utilize PROM, SRAM on chip address latches
- Invert "ALE"

3.4 IOU Gate Array Manchester Encoder/Decoder:

Refer to soft macros "UTBMANE" and "UTBMAND" for more details.

The Vendor macro:
- Manchester II
- 1553B like
- 20 Bit Words (sync character 3 bits, Data 16 bits, and Odd parity 1 bit)
- 1 MBPS Bus (Raw data rate)
- Runs off transformer coupled AACS Bus A or B
IOU Application Specific
- Local echo
- FIFO control
- 80C85 Read/Write control (INTCS, CTWBUS and CTRBUS)
- AACS bus time out (TOB)
- AACS Bus write protect (BUSWP)

3.5 IOU Gate Array Bus Select & AACS Bus I/F:

Select AACS Bus A or B
- Select controlled by command SYNC word or IOU F/W (If F/W not overriden by BC IOU command)
Generate configuration clock (CFGCLK) if good Manchester word decoded (Allow IOU config. change if no parity errors)
Respond to F/W AACS bus write protect (BC IOU uses this to prevent reply packet changing BC IOU configuration)
Provide select status (running on A or B)
AACS Bus I/F A & B circuit - transformer coupled transceivers

3.6 IOU gate Array User I/F

Function
- Provide interlocked Read/Write control of User Electronics
- Generate User:
  - Address (8 bits)
  - Write Data (8 Bits)
  - Read and Write Request

3.6 IOU Gate Array User I/F (cont'd)

Function
- Pickup User Read data (8 Bits)
- Detect Read or Write acknowledge - Cycle Complete

3.7 IOU Gate Array Discrete I/O

Function
- Provide general purpose signals
- 2 Discrete Signals In - Used to read status of the 2 discrete signals out
- 2 Discrete Signals Out - Used to:
  - Enable transmitter
  - Enable detection of illegal, simultaneous transmission on AACS Bus A, B (babble detector).
- All 4 were added when final gate aray design yielded 4 spare pins.

3.8 Worst-Case Timing

3.8 Worst case timing specification and timing diagrams:

Note: The following worst case timing parametes are derived from the "Slow simulation" (condition "D") and provided here as a user reference and they represent a superset of parameters presented in Sec. 5.5 under AC characteristics. The parameters stated in Sec. 5.5 takes into account the necessary guard bands for Trillium tester which is not reflected here.

Table 3-2. IOU Gate Array Worst Case Timing Specifications

* These parameters are guarenteed by design but not necessarily tested. Refer to Sec. 5.5 "AC Characteristics" for the AC parameters tested by the Vendor.

The following timing diagrams are provided for user reference to understand various cycles of this gate array.

Worst-Case Timing (continued)

Timing Diagrams: There are over a dozen timing diagrams in the IOU gate array specification describing various modes of operation including:

AACS RT IOU/USER I/F Timing
Local Echo Enable Write
Status Read Cycle
UserIF Write Cycle
UserIF Read Cycle
SRAM Write Cycle
STAM Read Cycle
PROM Read Cycle
Zero Crossing Deviation +150 on Manchester
Status Read-Valid Word Manchester
Zero Crossing Deviation -150 on Manchester
Status Word Read -Valid Word Manchester

We have only shown three important timing diagrams for your reference here. On this page we show the AACS RT IOU/User Interface (I/F) Timing. On the following page we show the Status Read Cycle and Local Echo Enable Write diagrams. These are representative of good timing diagrams and show the significant functional activity relative to important clock and control signal changes.

User Interface (I/F) Timing
Status Read Cycle and Local Echo Enable Write diagrams

4. TESTABILITY CONSTRUCTS

The "Testability Constructs" section should describe any of the structure design-for-test (DFT) methodology used for the core an ASIC device as well as for its I/O ring. Example DFT techniques for the core and ASIC device include:

Full or partial scan
LSSD (Level Sensitive Scan Design)
BIST(built-in self test)
Random Access scan
Set scan, etc.

For the I/O ring, an emerging standard is IEEE 1149.1 boundary scan approach. Please refer to the guide's Section Three: Chapter 3, on DFT details.

For the IOU gate array, full scan is used internally to aid in increasing overall fault coverage and its I/O signals have an IEEE1149.1-like boundary scan implementation. A NAND tree is implemented in the IOU gate array to facilitate V_il and V_ih DC tests. A NAND tree is an approach for I/O characterization recommended by several ASIC vendors. Inclusion of a NAND tree in your ASIC design makes the generation of DC test vectors a simple task.

4.0 TESTABILITY CONSTRUCTS

4.1 Use of Scan: All of the latch elements used in the core area have scan capability. They are implemented using a multiplexer in front of every latch element to accept either system data or scan data. Scan elements are used to aid in increasing the overall fault coverage for IOU gate array. They are specially useful in dealing with long counter chains and to access and control some buried nodes. At the package level, there are several scan signals as described in Table 2-1 and listed below. They may appear to be in the same format as JTAG (IEEE-1149.1 standard for boundary scan), but this appearance is coincidental. There is no JTAG implementation on this device.

Scan Signals:

SDIN - Scan Data In
SDOUT - Scan Data Out
SCNCLK - Scan Clock
SE - Scan Enable
BUFOFF - Scan Path

4.2 NAND Tree for DC Tests: To facilitate DC tests such as V_IL and V_IH, a NAND tree connecting all input pads and bidirectional pads (configured in input mode) is implemented on this gate array in accordance with the Vendor requirements. Refer to the vendor manual on "DC TESTING USING TREE CIRCUITS" for more details. "TESTDC", I/O pin #24 is assigned for NAND tree test.

5. ELECTRICAL CHARACTERISTICS

5.1 Electrical Test Requirements:

This section is put together by the parts specialist. Most of the sub- sections are self explanatory.<

Electrical Test Requirements: This table reflects all the applicable subgroups per MIL-STD-883 concerning pre-burn-in, post-burn-in, post 240 hour burn-in, etc.

5. Electrical Characteristics

5.1 Electrical Test Requirements

Table 5-1. Electrical Test Requirements

* PDA applies to these subgroups.

** Delta limits of Table VI herein shall apply.

*** Subgroup 4 (Cin and Cout measurements) shall be measured only for initial qualification and after process or design changes which may affect the value.

**** Group B.5 life test shall be performed using the dynamic burn-in configuration of fig. 3 herein. The table VI delta limits shall apply to the life test only.

Absolute Maximum Ratings:

This is a standard table indicating the values for various condition under which a device's operating characteristics will not degrade excessively. These values are independent of each other. Simultaneous application of these conditions may cause a device to fail prematurely.

Recommended Operating conditions:

This standard table, "Maximum Operating Frequency," should reflect the maximum frequency at which the device can operate. keep in mind that "fMAX" may be different than the target system speed.

5.2 Absolute Maximum Ratings

Table 5-2. Absolute Maximum Ratings

* ESD test method conforms to MIL-STD-883C, Method 3015, Electrostatic Discharge Sensitivity Test.

** This value is measured per Method-1012.

Note:

All voltages are referenced to VSS.
Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

5.3 Recommended Operating Conditions

Recommended Operating Conditions

5.4 DC Electrical Characteristics

This section lists all DC parameters guaranteed by the ASIC vendor. You should be able to extract this section out of the vendor's library/ design handbook. You may want to modify it as it applies to your ASIC design.

For example, if you are not using a triple-drive buffer in your design, you may want to leave it out of your list.

All exceptions and special conditions under which the device will be tested should be listed as footnotes.

5.4 DC Characteristics

5.4.1 DC Electrical Performance Characteristics

DC Electrical Performance Characteristics Table 5-4 DC Performance Characteristics

* Contact The Vendor prior to usage.

** If I_OL and I_OH exceed the max. limits for CMOS outputs, V_OL and V_OH will vary according to the sink or source current vs. V_OL and V_OH curve supplied by The Vendor.

Notes:

Supplied as a design limit but not guaranteed or tested.
Not more than one outpt may be shorted at a time for a maximum duration of one second.
Capacitance measured for initial qualification or design changes which may affect the value.
I_OS CMOS equals I_OS single-drive buffer.
Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions:
a. V_IH = V_IH(min) + 20%, -0%; V_IL = V_IL(max) + 0%, -50%, as specified herein, for TTL - or CMOS - compatible inputs.
b. Devices may be tested using input voltage within the above specified range, but are guaranteed to V_IH(min) and V_IL(max).
All input and output buffes including the bidirect buffers are identified on page #12.
Iddq is measured at V_DD = 5.5V and at three temperature conditions namely, T_A (ambient temperature) at -55^oC, 25^oC and 125^oC.
Iddq_all is a quiescent supply current limit for Iddq testing as described in sec. 5.4.2. This limit is used as a GO/NO GO limit and it is subject to change after characterization. Iddq testing will be done at 25^oC and V_DD = 5.0V.

5.4.2. I_DDQ Testing:

This section is applicable only if I_DDQ test vectors and conditions under which ASIC devices will be tested for I_DDQ should be explicitly stated. for more information on I_DDQ testing , please refer to Section Four: Chapter 1 of the Guide.

Pull-down and pull-up resistors: If you are using any internal pull- up and/or pull-down resistors, they should be listed. If I_DDQ testing is one of your requirements, use any pull- ups or pull-downs in the core of an ASIC or in I/Os is highly discouraged as it makes the high-resolution current measurements required difficult or impossible.

5.4.2 I_DDQ Testing.

Quiescent Current (I_DDQ) testing shall be accomplished by using as close to 100% "Node Toggle Vectors" as possible which can be derived from the functional vecotrs or through a process determined by The Vendor and approved by JPL. Measurement stop points will be identified by JPL. I_DDQ testing will be a GO/NO GO test. A single stop point shall be established for read-and-record measurements and delta calculations. The I_DDQ limit is subject to change after device characterization. Refer to contract provisions for any exceptions to the qequirements stated here and I_DDQ test program development, limits and screening of flight parts for I_DDQ.

5.4.3 Pulldown Resisters.

Certain input pins are required to be held to a logic low state in flight.

SE
TESTDC
SDIN
SCNCLK
BUFOFF
SIMPOR

There are no internal pull-down resistors used.

5.4.4 Pullup Resistors.

There are no internal pull-up resistors used.

5.5 AC Electrical Characteristics:

This section contains some of the most important information sources for an ASIC vendor to screen ASIC devices; users find it valuable for application of a device.

AC Electrical Performance Characteristics:

All AC parameters of importance should be listed here. The table should also state the vector sets to be used along with electrical and thermal conditions. These numbers should reflect the vendor's tester guard bands.

5.5.1 AC Electrical Performance Characteristics

AC Electrical Performance Characteristics
Table 5-5. AC Performance Characteristics

Note:

All "Functional tests @1 MHZ" and all "At speed tests @12.5 MHZ" must pass at V_DD = 4.5V, 125^oC and at V_DD = 5.5V, -55^oC.
For AC tests using input pin C12MHZ, the actual delay is the spec. limit minus either 100ns or 600ns to account for the delay in input transitions in the tester cycle.

5.5.2 Timing Analysis:

This analysis is a discipline for ensuring a design shows correct timing behavior.

5.5.2 Timing Analysis.

Pre-layout and post-layout timing margins shall meet the contractor's requirements for timing analysis. Refer to "Additional Requirements" on page #6 for more details.

5.5.2.1 Pre-Layout Timing Margins.

Pre-layout timing margins shall be calculated by using standard extremem-value analysis. The extreme values for the cell library were supplied by The Vendor. Critical paths were identified before layout and margins were calculated via Valid or The Vendor software toolsets, or a combination thereof.

5.5.2.2 Post-Layout Timing Margins.

Post-layout analysis of the device shows positive margin on internal critical paths over all operating conditions. The analysis follows the same form as the pre-layout analysis, with the post-layout timing values annotated to the design file by the contractor. Timing parameters listed in Sec. 5.5 under AC characteristics are derived from post-layout data using actual wire lengths.

5.5.2.3 Tester Specification Limits.

Tester Specification limits in Table 5-5 have been adjusted for modified output levels and for differences in output loading in the Trillium tester environment. Modified output levels are required to account for impedance mismatches between device outputs and the Trillium tester environment. Refer to Figure 5-3 for switching test circuits and waveforms.

5.5.3 Switching Test Circuit:

This circuit is obtained from the vendor's handbook and it is usually a standard circuit.

Figure 5-3. Switching test circuits and waveforms

Note: This capacitance is actually partially distributed through the fixturing so that the device is actually loaded by a transmission line.

5.6 Burn-In:

Table 5-6 represents the static and dynamic burn-in strategies allowed for the IOU gate array. These strategies are driven by your parts and/or Q/A group and are dependent on the vendor's burn-in capabilities and limitations.

5.4.1 Static Burn-In

The Static Burn-In conditions per MIL-STD-883 Method 1015 shall be as specified in JPL General Specification CS The Cassini ASIC Boilerplate Spec, Rev. C. The burn-in configuration shall be as shown in Table 5-6.

5.4.2 Dynamic Burn-In

The Dynamic Burn-In conditions shall be as specified in JPL General Specification CS the Cassini ASIC Boilerplate Spec, Rev. C. The burn-in configuration shall be as shown in Table 5-6.

Table 5-6. Burn-in Connections

Notes:

Unless otherwise specified, condition shall be 6.0V <= VDD <= 6.5V, -0.5V <= GND <= 0.5V, VIL <= 0.8V, VIH >= 2.2V, VDD = 6.0 Volts for life test only.
All inputs and outputs are connected through a 2.5K ohm +/-5%, 1/4W resistor. Power and Ground pins are directly connected to power and ground or some of the pins may be connected through a 2.5K ohm resistor to power and ground.
f_o = 200KHZ, f_n = (f_n-1)/2 where n >= 1; Duty Cycle = 50% +/- 15%.
IN = Input, OUT = Output, I/O = Input/Output (bidirect), Tri = output tristate.

5.6.4 Delta Limits:

These limits are usually +/- 10 percent of the specification limits and are also available from the ASIC vendor.

Table 5-7. Delta Limits

* Delta limits will be -10% of the min. values.

** Subject to change after device characterization.

Refer to page #12 for description of various input, output and bidirect drivers/buffers used for this gate array.
If I_OL and I_OH exceed the max. limits for CMOS outputs, V_OL and V_OH will vary according to the sink or source current vs. V_OL and V_OH curve supplied by The Vendor.

6. PHYSICAL CHARACTERISTICS

6.1 Pin Assignment

This is given by the ASIC designer and approved by the vendor. The vendor checks into pad placement, simultaneously switching outputs, etc.

IOU ASIC Pinout Assignments

6.2 Bonding Diagram:

This is supplied by the ASIC vendor.

Any exception to the standard vendor bonding diagram should be highlighted and approved by the ASIC vendor.

Bonding Diagram:

6.3 Package Outline:

This information is supplied by the vendor and is used for required board area estimation and fabrication set up.

Package Outline

Connection Table:

This table is used as a comprehensive record of all ASIC assembly interconnections.

Connection Table
Table 6-1. Connections Table

(This is a die pad to bondfinger to package pin connection table for a 84-lead top-brazed flatpak)

Notes:

All VDD bondfingers are connected to the power plane, die-attach pad and external leads 84 and 43.
All VSS bondfingers are connected to the ground plane and external leads 1 and 42.

6.4 Marking Diagram

This diagram is laid out by the parts specialist.

Fig. 6.4 Marking diagram

(1) The Vendor Part Number
(2) QPL Number (for flight unit only)
(3) Customer Part Number
(4) The Vendor Trademark
(5) Federal Supplier Manufacturing Number
(6) Country of Origin
(7) Pin 1 indicator and ESD identifier
(8) Date code - Year and Fiscal Week of Lid Seal. YY = Year, FW = Fiscal Week, and A = Identifier for lots sealed within same week. ( A - designates the second assembly lot of devices sealed within FWXX, B designates the third assembly lot of devices sealed within FWXX etc. The first assembly lot of devices sealed does not have a designator.)
(9) Serialization (Traceability Capability to Die)
(10) Chip Name

7. DEVICE STATISTICS

This information contains some major statistics derived from the design verification report. Device statistics information is optional and not always required.

-  Total Port signals			76

	Inputs				32
	Outputs				28
	Bidirects			16

-  Total VSS and VDD pins		8

-  Cell and block counts:

				Local	Global
		   Cells	131	1921
		   Blocks	231	13047

-  p and n-transistor counts:

			p: 13486	n:13399

-  Number of gates:			5624

-  Full internal scan

- Scan port signals provided to facilitate internal scan but there
   is no JTAG 1149.1 implementation.

-  NAND tree implemented for DC tests.

-  Functional patterns @1MHZ are used to achieve 98.1% Port fault
   coverage with ac delay measurements.

-  84 pin ceramic flatpack

8. EXCEPTIONS TO THIS DOCUMENT

The CS document is the base document used for procurement of QPL/QML devices. These controlling documents are under constant revision and may need some exceptions for viable procurement of your ASIC.

The following are the applicable exceptions to The Cassini ASIC Boilerplate Spec.

Sheet-3, Section 2.1 APPLICABLE DOCUMENTS
Change "MIL-M-38510M" to "MIL-M- 38510".
Change "MIL-STD-883C" to "MIL-STD- 883".
Use Test method 1019.4 without TDE since it is specified and approved.
Sheet-6, Section 3.8 JPL REVIEW OF MANUFACTURER'S DOCUMENTATION
Subparagraph a: The Vendor does not normally provide information regarding yield data. For QCI, The Vendor will provide summaries. Since group D is generic data, copies of the travellers are unnecessary.
Subparagraph b: Delete JPL approval rights since it has been agreed that JPL accepts The Vendor test tapes, but reserves the right to review them. The Vendor will provide a copy of the test flow chart, a detailed test module description, test program binary on tape, a copy of the test generation summary file, the test program execution summary file and will permit review of the test program source code and flow with JPL at the Vendor facility.
Section 3.10 PROBLEM NOTIFICATION
Under Subparagraph 3.10.a: The Vendor will inform JPL at interim and post purn-in room temperature test failures.
Sheet-7, Section 4.3.4. TEST METHOD DEVIATION
Delete this paragraph since The Vendor processing flows are defined and controlled and no deviations are expected. JPL may review these flows at any time.
Sheet 8, Section 4.3.6. TEST EQUIPMENT VERIFICATION
The Vendor uses a single golden unit with sufficient controls in place to obviate the need for three control units. Thus, in this paragraph all references to three control units are chaged to one.
Sheet-8, Section 4.5.1. QCI - GENERAL
The Vendor does supply a complete traveller, however, the lot specific traveller can be reviewed by JPL on-site.
Sheet-8, Section 4.5.6. QCI - GROUP E INSPECTION
Change "100 rads (Si) /s" to "100-300 rads (Si) /s".
Sheet-10, Section 4.8.1.a. SCREENING TEST DATA FOR CLASS S MICROCIRUITS
The completed lot traveller can be reviewed by JPL on-site at The Vendor.

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