Objective:
To provide ASIC managers and designers a
method of mapping a set of system and organizational requirements
into a detailed set of device functional, performance, and test
specifications.
A well-written ASIC specification creates an
unambiguous ASIC device description that guides the ASIC designer's
development work, the ASIC vendor's manufacture, test and
screening work, and the system implementor's work. Using this
description, which may exist at many levels, ASIC program managers
can measure the technical progress of the ASIC design. The
specification also forms the basis for contracting and procuring the
ASIC parts.
Generally, the ASIC designer and a parts specialist jointly create a
detailed technical specification. Once generated, the design team
negotiates the specification with the ASIC vendor for any exceptions
that a vendor may choose to take. Besides the ASIC designer, any
ASIC device user needs this document. We recommend that it
provide the kind of information typically found in any standard VLSI
parts handbook.
We limit the focus of this chapter to the technical specification.
Please refer to the management section and the procurement support
appendix for information on other types of contract information. The
guide's Appendix Six shows a
technical specification case study of one of the gate arrays used in
the JPL Attitude and Articulation Control Subsystem for the Cassini
spacecraft. Below, we will discuss major areas of an ASIC Technical
Specification.
The "Scope" section of the technical specification provides
a clear definition of the document, including what the specification
covers and how to use it.
The list of "Applicable Documents" together with the
technical specification contain all requirements levied on the ASIC,
such as government documents, NASA center or prime contractor
documents, vendor documents, and the project requirements.
"Conventions" covers any special notation used to make
the technical specification easier to read and understand. This part
of the specification usually refers to the conventions used for signal
names.
This section contains technical specifications not covered in the other
sections of the technical specification document and may include CAD
tools, processing, packaging areas, etc.
This section offers a brief description of the ASIC's functions and
features. It also includes a block diagram of an ASIC device and how
it may fit into its intended target application.
This part of the specification provides a pin-out and pad designation
(useful when probing--but not a must), type of a signal (input,
output, tri-state, etc.), its drive when active, I/O receiver and driver
macro names, and signal description.
The "Functional Description" describes ASIC functions in
detail. As a specification typically describes an ASIC design in a
hierarchical fashion to ease of understanding and verification,
describe each module and sub module in detail including control and
data flow. Also describe any internal buses, any internal registers,
all internal and external timing diagrams, various modes of
operations and external interfaces, and define all acronyms used.
Use this section to point out any testability features implemented to
make a device more testable. Describe the list of I/O signals (if
applicable) used to implement boundary scan. To facilitate DC tests,
also specify here all testability enhancements, such as synchronous
full scan, partial scan, built-in self-test methods, and NAND tree
approach.
This portion of the specification concerns various parameter limits
and how they can be used, measured, and verified, including:
List all required burn-in tests, how delta limits are calculated per
MIL-STD-883, and applicable subgroups in "Electrical Test
Requirements."
The vendor usually has this section readily available. It states the
absolute electrical and thermal limits to which a device can be
subjected and that a vendor will guarantee. Designers must calculate
maximum power dissipation and maximum output current as they
will vary from ASIC to ASIC. The project drives the electrostatic
discharge voltage (VESD) requirement, which must to
comply with vendor's capability.
The vendor data books on cell characteristics can provide this part of
the specification, excepting the device dependent maximum
operating frequency parameter.
This section lists all vendor guaranteed DC parameters such as
VIL, VIH, VOL, VOH,
IOZ, IOS, CIN and COUT
parameters. Use this section to point out any exceptions or any
special condition concerning device testing.
If your project requirement calls for negotiating with the vendor
IDDQ testing of ASIC devices, source of the test vectors,
the number of measurement points and measurement limits for
IDDQ, explicitly state that here. If your device requires
IDDQ testing, avoid using pull-up or pull down resistors
altogether, since use of such resistors will reduce the amount of
toggle coverage during IDDQ testing.
List all pull-up or pull-down resistors used either internally or for
I/Os here. Also list any signals which, for example, may have been
used for testability enhancement and must be held either in low or
high state during flight.
Based on the simulation results signed off at Critical Design Review
(CDR) time, the ASIC vendor will guarantee all functional testing at
slow speed (typically at 1 or 2 MHz) and "AC tests" at
system speed under extreme voltage and temperature conditions.
Make sure the vendor checks and screens any parts not meeting
critical timing parameters, such as, propagation delays, setup and
hold times and pulse widths with either minimum or maximum
limits. Adjust all AC parameters for modified tester output levels
and loading. Also describe applicable switching test circuits.
The parts specialist defines and negotiates with the vendor on
various static and dynamic burn-in conditions, as well as terminal
connections.
Establish these limits per MIL-STD-883, for parameters such as input
and output leakage currents (in high and low states) for all used I/O
buffers, sinking and sourcing currents for output buffers, output low
and high voltage levels, and for quiescent current.
This section contains information on pin assignment, bonding
diagram, package outline, and marking diagram.
Taking number of simultaneously switching outputs per
VSS/VDD pair into account, the ASIC designer
comes up with a preferred pin assignment, obeying rules imposed by
the vendor for power and ground pins placement. The vendor must
approve this preferred assignment before it can be incorporated into
the specification.
This diagram shows the package pin-to-die pad assignment. Some
vendors will have a fixed assignment that a designer has to use;
other vendors will give some freedom in this assignment.
The vendor provides the package outline information, which shows
all mechanical dimensions and tolerances.
Produce this diagram according to MIL standard documents for
marking diagrams. Besides information such as part number, date
code, pin number 1 indicator and ESD identifier, etc., include
traceability capability to die information.
This provides a quick glance at device statistics such as total number
of used gates, number of input, output and bi-direct signals, use of
testability constructs, package type, fault coverage, etc.
Negotiate any variations and deviations that may apply to documents
mentioned earlier in this chapter with the vendor and list them in
this section.
Summary
- The ASIC designer and his manager take responsibility for the
technical specification. While they should seek appropriate help
from others, the final responsibility must remain with them.
- Technical specifications amount to much more than paper
descriptions of a circuit, completed mainly after the vendor delivers
a chip. The many roles a technical ASIC specification may fill
include:
- a contract between ASIC manager and designer(s), which defines
designers' deliverables
- a detailed "data book" for other device users
- the important contract between the ASIC design group and any
other internal (quality assurance, test, reliability, etc.) or external
(ASIC vendor) groups
- A complete technical specification must include all applicable
documents (see Appendix
Six), so the reader can find further information on any particular
subject.
- Remember the technical specification is part of a contract package
including the general contract and the statement of work (SOW).
Keep all three contracts in mind when creating the technical
specification. Try to support procurement by integrating the
technical specification with them. This will also reduce potential
errors that the ASIC vendor may generate in translating your
technical specification into their own internal circuit and device
descriptions.
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