List of Tables and Figures

Tables

3-1. Room-temperature properties of GaAs 17
3-2. Epitaxial layer compositions for basic GaAs-based HEMT and PHEMT devices compared with those of MESFET 41
3-3. Comparison of AlGaAs/GaAs HBT and Si bipolar transistors 44
3-4. Matrix of solid-state devices and their applications in MMICs 76
4-1. Common MMIC failure modes 89
4-2. General responsibilities for the failure-mechanism categories 92
5-1. Relationship between variations of bias and element values 120
7-1. Common parametric monitors 133
7-2. Typical test structure information 134
7-3. Examples of dc and RF autoprobe test parameters 135
8-1. Typical packaged device screening 162
9-1. Summary of reliability test conditions and results for fluxless flip-chip thermocompression-bonded bump contacts 185
10-1. Total-dose tolerance of various GaAs MMIC devices 228
10-2. Ion-bombardment-induced degradation of drain current in GaAs devices 236
10-3. Characteristics of four GaAs microwave transistors examined for SEB 238

Figures

2-1. Semiconductor cumulative failure distribution 6
2-2. Product development cycle 6
2-3. Probability of survival to time t, for a constant failure rate 9
2-4. Probability of success normalized to the MTBF 10
2-5. Semiconductor failure rate 10
2-6. Arrhenius plot 12
3-1. Unit cube of GaAs crystal lattice 16
3-2. Energy band diagram for GaAs 17
3-3. Energy band structure of Si and GaAs 18
3-4 Drift velocity of electrons in GaAs and Si as a function of the electric field 19
3-5. Energy band diagram of GaAs with impurities 22
3-6. Schematic and cross section of metal–GaAs junction 25
3-7. Energy band diagram of metal and semiconductor separate and in contact 25
3-8. Energy band diagram of metal–semiconductor junction under forward bias and reverse bias 26
3-9. Energy band diagram of metal and semiconductor separate from each other when semiconductor surface states exist 27
3-10. Energy band diagram of metal–n+ semiconductor junction and metal–semiconductor junction under reverse bias 30
3-11. GaAs planar diode 31
3-12. Schematic and cross section of a MESFET 34
3-13 Schematic and I–V characteristics for an ungated MESFET 35
3-14. Minimum band-gap energy vs lattice constant data for III–V semiconductors 40
3-15. Epitaxial structure of a basic AlGaAs/GaAs HEMT 40
3-16. Energy band diagram of a generic AlGaAs–GaAs HEMT showing the 2DEG quantum well channel 41
3-17. Cross section of an example HBT 45
3-18. An HBT cross section showing a thin ledge of AlGaAs 46
3-19. AlGaAs/GaAs HBTs 47
3-20. Typical I–V characteristic of a power HBT with multifinger design 49
3-21. pnn fabrication from HBT structure 51
3-22. pnn diode 52
3-23. Two resistor types in MMIC fabrication 57
3-24. MIM capacitor using an air bridge for top-level interconnect 59
3-25. Spiral inductors 60
3-26. Transmission lines 61
3-27. Ideal via hole in GaAs 62
3-28. Air bridge connecting coplanar waveguide ground planes 62
3-29. Basic sequence of process steps 64
3-30. Basic process steps for MESFETs 65
3-31. Basic process steps for GaAs, AuGeNi, and TaN resistor 66
3-32. The air-bridge process 67
3-33. Via hole with process-variable parameters 67
3-34. Typical HEMT/PHEMT process flow 69
3-35. A typical HBT device processing sequence 71
3-36. Self-aligned HBT cross-sectional view 73
3-37. Schematic cross section of the self-aligned HBT IC structure 73
3-38. Schematic of microwave receiver 74
3-39. Schematic of microwave transmitter 74
3-40. 30-GHz MMIC receiver 75
3-41. Output power as a function of input power for a typical amplifier 77
3-42. 20-GHz high-power amplifier 79
3-43. Schematic of simple mixer 81
3-44. Mixer diode I–V characteristics 82
3-45. Schematic of oscillator 83
3-46. Power spectrum for a typical oscillator 84
3-47. Schematic of reflective-type phase shifter 85
3-48. Analog phase shifter comprised of a varactor-tuned reflective load and a Lange coupler 86
3-49. Phase shifter comprised of loaded-line and switched-line sections 87
3-50. 22.5-deg phase-shifter elements 88
4-1. Schematic cross section of a MESFET with different surface charges 94
4-2. Metal-atom migration and accumulation 96
4-3. Depletion and accumulation of material in AuGeIn source and drain ohmic contacts 97
4-4. Schematic cross section of a degraded MESFET 99
4-5. Blown-out gate recess 100
4-6. SEM photograph of a failed nickel–chromium resistor 101
4-7. Edge-located ESD failure of a MIM capacitor 102
4-8. Interior-located ESD failure of a MIM capacitor 103
4-9. Filamentary growth 104
4-10. Changes in peak transconductance and drain current at zero gate bias of InP HEMT and GaAs PHEMT 105
5-1. Flow chart of the relationship between characterization, parameter extraction, and modeling 109
5-2. Schematic of a MESFET’S material and structure 111
5-3. Basic GaAs MESFET’s equivalent circuit 111
5-4. Flow chart of dc modeling 114
5-5. Small-signal direct model extraction process for S-parameter measurement at multiple frequencies 115
5-6. Typical flow chart of characterization and parameter extraction for large-signal model 116
5-7. Flow chart for MMIC sensitivity analysis 120
5-8. Application of the Monte Carlo method to MMIC yield forecasting 121
6-1. Typical design flow 129
7-1. TCV example 132
7-2. Example of parametric-monitor locations across the wafer 133
8-1. Recommended qualification methodology 138
8-2. Reliability audit 140
8-3. MMIC die process qualification 147
8-4. MMIC process reliability evaluation 148
8-5. MMIC design validation 150
8-6. GaAs part qualification overview 157
8-7. Lot acceptance test for die 158
8-8. Wafer acceptance test 160
8-9. Screening process for packaged MMICs 161
9-1. 20- to 40-GHz ceramic MMIC package 171
9-2. Prototype of a four-element antenna package 171
9-3. MMIC package 173
9-4. Cross section of MMIC attached to a package and its equivalent thermal circuit 176
9-5. GaAs MMIC switch matrix in a metal package 177
9-6. 20-GHz receiver in a metal package 177
9-7. Schematic of thin-film multilayer package with integrated MMICs 180
9-8. GaAs MMIC in compression 181
9-9. The presence of voids in the die-attach material 182
9-10. Bonding material 183
9-11. Flip-chip package 184
9-12. Copper diffusion in polyimide 188
9-13. Self-gettering of Cu changes line geometry 188
9-14. Stress cracks in polyimide at via holes 188
9-15. Typical plastic package showing the onset of a crack 190
9-16. Mold compound properties 191
9-17. Polyimide die overcoat (PIX) on MMIC die 191
9-18. Typical geometry of wire bond with different die settings 192
9-19. Multilayer ceramic package with metallized frame walls 194
9-20. Ceramic package with metal-filled vias 195
9-21. Measured and modeled S-parameters 196
9-22. Computed vertical electric-field distribution 197
9-23. Partially filled metal cavity with microstrip input/output ports 198
9-24. Percent change in pinch-off voltage 201
10-1. Schematic diagram of the Earth’s Van Allen radiation belts 204
10-2. World map contours of electron dose at 500 km 205
10-3. Sunspot activity and solar flare events for solar cycles 19, 20, and 21 206
10-4. Distribution in energy and abundance of various galactic
cosmic ray particles 207
10-5. Attenuation of galactic cosmic ray Si ions 208
10-6. Van Allen belt trapped proton spectra emerging from spherical shields
of various thicknesses for a 500-km orbit at 60-deg inclination 209
10-7. Ionizing-dose failure levels for MOSFET integrated circuits 212
10-8. Ionizing-dose failure levels for bipolar integrated circuits 213
10-9. Ionizing-dose failure levels for discrete, linear, and digital device families 214
10-10. Primary photocurrent magnitudes generated by prompt dose-rate irradiations in various types of diodes 215 10-11. Prompt ionizing dose-rate hardness levels for bipolar and MOS integrated circuit families 216
10-12. Prompt ionizing dose-rate hardness levels for discrete device families 217
10-13. Neutron hardness levels for discrete devices 219
10-14. Neutron hardness levels for integrated circuit families 220
10-15. Single event upset in a typical SRAM memory cell 221
10-16. Dependence of critical charge for upset on feature size for various integrated circuit technologies 222
10-17. SEU rates at geosynchronous orbits for various circuit technologies 224
10-18. Change in saturation current of enhancement mode GaAs JFET after irradiation 228
10-19. Cross section of GaAs JFET showing transient ionization-induced back-gating effect 229
10-20. Transient response of drain current to 20-ns electron pulses for GaAs JFETs on two types of substrates 230
10-21. Transient drain current response for single- and double-implanted GaAs JFETs 230
10-22. Peak-to-peak power upset generated by 50-ns pulses of 40-MeV electrons bombarding TI two-state feedback amplifier MMICs 231
10-23. Response of MMIC amplifiers to transient electron pulses 232
10-24. Neutron fluence necessary to reduce JFET transconductance by 20% in n-type GaAs and Si 233
10-25. Gain degradation of several types of bipolar transistors 234
10-26. Effect of neutron irradiation on TI GaAs FET parameters 234
10-27. Response of two GaAs MMIC amplifiers to neutron irradiation 235
10-28. Single-particle-induced charge collection mechanisms in a GaAs MESFET 237