Index

A

• Accelerated stress testing: Appendix 7
• Access time: Section 4: Chapter 2
• Addressable storage elements: Section 3: Chapter 3
• Altered item drawing: Section 4: Chapter 1
• Annealing: Section 3: Chapter 4
• Architecture: Section 3: Chapter 2, Section 3: Chapter 2
• ASIC
  • advantages: Section 1: Introduction
  • cell emulation: Section 3: Chapter 2
  • contracting: Section 1: Chapter 1
    • intra-organizational: Section 1: Chapter 1
    • with the vendor: Section 1: Chapter 1
  • contrasted to off-the-shelf devices: Section 1: Introduction
  • deliverables: Appendix 5
  • development: Section 4: Chapter 2
  • development cycle: Section 2: Chapter 5
  • equipment and tool planning: Section 1: Chapter 2
  • fabrication: Section 1: Chapter 2, Appendix 1
    • process development: Appendix 1
  • management
    • activities: Section 1: Introduction
    • evaluation: Section 2: Introduction
    • of ASIC development tasks: Section 1: Chapter 1
    • planning steps: Section 1: Chapter 2
    • skills background: Section 1: Introduction
  • manufacturing: Section 1: Chapter 1
  • processes: Section 1: Chapter 1
  • program
    • ASIC program flow: Section 1: Chapter 1
    • bottlenecks: Section 1: Chapter 2
    • budgeting: Section 1: Chapter 2
    • example schedule: Section 1: Chapter 2
    • modeling flow. See Modeling: ASIC program modeling flow
    • planning: Section 1: Chapter 1
    • resources: Section 1: Chapter 2
    • reviews: Section 1: Chapter 5
  • quick look at ASIC flow major processes: Section 1: Chapter 1
  • resource planning: Section 1: Chapter 2
  • setting requirements: Section 1: Chapter 1
  • size: Section 3: Chapter 3 , Section 3: Chapter 3, Section 3: Chapter 3
  • system partitioning: Section 1: Chapter 1
  • tasks
    • major: Section 1: Chapter 2
  • trade-offs: Section 1: Chapter 1
• Automatic test pattern generation (ATPG): Section 3: Chapter 2 , Section 4: Chapter 4 . See also Design: automatic test pattern generation

B

• Back annotation: Appendix 1
• BILBO: Section 3: Chapter 3
• Bonding diagram: Appendix 6
• Boundary scan: Section 3: Chapter 3 , Appendix 1 , Appendix 1
  • benefits and penalties: Section 3: Chapter 3
  • cells: Section 3: Chapter 3
  • design: Section 2: Chapter 3
  • example: Section 3: Chapter 3
• Breadboard: Section 3: Chapter 2
• Bridged interconnect: Section 4: Chapter 1
• Budgeting an ASIC program. See ASIC: program: budgeting
• Buffering: Section 3: Chapter 2
• Burn-in: Section 4: Chapter 1 , Section 4: Chapter 3 , Section 4: Chapter 3 , Section 4: Chapter 3
  • dynamic: Section 4: Chapter 3
  • specification: Section 4: Chapter 3
  • static: Section 4: Chapter 3
• Bus lines: Section 3: Chapter 2
• Bus routing: Section 3: Chapter 2

C

• CAD: Section 3: Chapter 2, Section 4: Chapter 2
  • tools: Section 2: Chapter 5
• Cell library: Section 2: Chapter 4, Section 4: Chapter 2
  • control and maintenance: Section 2: Chapter 4
  • data book: Section 2: Chapter 4
  • development: Appendix 1, Appendix 1
  • documentation: Section 2: Chapter 4
• Change control: Section 1: Chapter 4
• Characterization: Section 4: Chapter 1, Section 4: Chapter 3, Section 4: Chapter 4. See also Test: and characterization
  • advanced techniques: Section 4: Chapter 2
  • engineering part: ection 4: Chapter 2
  • specification of: Section 4: Chapter 1
  • system: Section 4: Chapter 1, Section 4: Chapter 2
• Chip sign-off review. See Review process: chip sign-off review
• Class
  • class B: Section 4: Chapter 3, Appendix 2
  • class Q: Section 4: Chapter 3
  • class S: Section 4: Chapter 3, Appendix 2
  • class V: Section 4: Chapter 3
  • QML and QPL part classes: Section 4: Chapter 3
• Clock buffering: Section 3: Chapter 2
• Clock signal: Section 3: Chapter 2
• Clock skew: Section 3: Chapter 2
• Clock trees: Section 3: Chapter 2
• Clocking: Section 3: Chapter 2
• CMOS-SOS: Section 3: Chapter 4
• Concurrent engineering: Section 1: Chapter 3, Section 1: Chapter 4
• Configuration control: Section 2: Chapter 5
• Configuration management: Section 1: Chapter 4
• Connection Table: Appendix 6
• Contingency planning: Section 1: Chapter 3. See also : Risk management: and contingency planning
• Contracting. See ASIC: contracting
• Controllability: Section 3: Chapter 2, Section 3: Chapter 3
• Correct-by-construction: Appendix 1
• Critical design review (CRD). See Review process: critical design review
• Critical paths: Section 3: Chapter 2
• Cross section for upset: Section 3: Chapter 4
• Current testing: Section 4: Chapter 1

D

• Data skew: Section 3: Chapter 2
• Defect: Section 3: Chapter 2, Section 4: Introduction, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 4
  • latent: Section 4: Chapter 1
  • physical: Section 3: Chapter 2
  • types of: Section 4: Chapter 1
• Degradation: Section 4: Chapter 1
• Delta measurements: Section 4: Chapter 2
• Department of defense (DoD): Appendix 2
• DESC: Section 4: Chapter 4, Section 4: Chapter 4, Appendix 2, Appendix 2.
• Design: Section 1: Chapter 1, Section 1: Chapter 2, Section 3: Chapter 2
  • analysis tools: Section 2: Chapter 5
    • critical path tools: Section 2: Chapter 5
    • power tools: Section 2: Chapter 5
    • timing tools: Section 2: Chapter 5
  • ASIC design systems: Appendix 1
  • ASIC management
    • designer support: Section 3: Introduction
  • capture tools: Section 2: Chapter 5
  • data base management: Section 2: Chapter 5
  • design rules: Appendix 1
  • experience: Section 3: Introduction
  • for producibility: Section 2: Chapter 2
  • for reliability: Section 2: Chapter 2
  • for test: Section 1: Chapter 3, Section 2: Chapter 3, Section 2: Chapter 5, Section 3: Chapter 3, Section 3: Chapter 3, Section 4: Chapter 4
  • for test, tools: Section 2: Chapter 5
    • automatic test pattern generation: Section 2: Chapter 5
    • test synthesis: Section 2: Chapter 5
  • logic design issues: Section 3: Chapter 2
  • logic synthesis and optimization tools: Section 2: Chapter 5
  • microelectronic: Section 3: Introduction
  • modeling and the design cycle. See Modeling: and the design cycle
  • partition tools: Section 2: Chapter 5
  • process: Section 3: Chapter 2
  • schedule: Section 1: Chapter 2
  • verification: Section 3: Chapter 2, Section 4: Chapter 1
    • chip model verification: Section 3: Chapter 2
    • design exploration: Section 3: Chapter 2
    • functional: Section 3: Chapter 2
    • non-destructive analysis: Section 3: Chapter 2
• Design cycle: Appendix 1
• Device (or process) learning factor: Appendix 7
• DFT. See Design: for test
• Die shear test: Section 4: Chapter 3
• Die-attach: Section 4: Chapter 1
• Doping profile: Section 4: Chapter 1

E

• EDA. See Electronic design automation industry: Appendix 1
• Electromigration: Section 4: Chapter 1, Section 4: Chapter 3
• Electronic design automation industry: Appendix 1
• Electrostatic discharge sensitivity: Section 4: Chapter 2
• End-of-life effects: Section 4: Chapter 3, Appendix 7
• End-of-line tests: Section 4: Introduction, Section 4: Chapter 4
• Engineering part: Section 4: Chapter 1
  • verification: Section 4: Chapter 2
• Environmental factor: Appendix 7
• epi: Section 3: Chapter 4
• Error detection and correction (EDAC): Section 3: Chapter 4
• Error rate: Section 3: Chapter 4
• Errors per bit day: Section 3: Chapter 4

F

• Fabrication. See ASIC: fabrication
• Failure analysis: Section 4: Chapter 3, Section 4: Chapter 3, Appendix 4
  • destructive examinations and tests: Appendix 4
    • cross-sectioning: Appendix 4
    • material analysis: Appendix 4
    • mechanical tests: Appendix 4
    • removal of layers: Appendix 4
  • failure confirmation examinations and tests: Appendix 4
    • electrical characterization: Appendix 4
    • external visual examination: Appendix 4
    • part failure history: Appendix 4
  • laboratory work flow: Appendix 4
  • major tasks: Appendix 4
  • nondestructive examinations and tests: Appendix 4
    • hermeticity tests: Appendix 4
    • particle detection test: Appendix 4
    • radiographic examination: Appendix 4
  • report: Appendix 4
  • semi-destructive examinations and tests: Appendix 4
    • electromechanical probing: Appendix 4
    • emission microscope test: Appendix 4
    • package gas analysis: Appendix 4
    • package opening and internal examination: Appendix 4
• Failure mechanism: Section 4: Introduction, Section 4: Chapter 3, Section 4: Chapter 3
• Failure rate: Appendix 7
• Fan in: Section 3: Chapter 2
• Fan out : Section 3: Chapter 2
• Fault coverage: Section 3: Chapter 2, Section 4: Chapter 1, Section 4: Chapter 1
• Fault detection and localization (FDL), IEEE PAR F. See Test: fault detection and localization, IEEE PAR f
• Fault models: Section 3: Chapter 2
  • at-speed functional: Section 4: Chapter 1
  • I_DDQ current faults. See I_DDQ testing
  • need for: Section 4: Chapter 1
  • stuck at fault. See Stuck-at fault
  • types of: Section 4: Chapter 1
• Feature size: Section 3: Chapter 2
• Field oxides: Section 3: Chapter 4
• Field programmable gate arrays. See FPGAs
• Field-oxide inversion: Section 3: Chapter 4
• Flight build review. See Review process: flight build review
• Flight part: Section 4: Chapter 1
  • verification: Section 4: Chapter 3
• Floor planning: Appendix 1
• Form: fit and function: Section 4: Chapter 2
• Formal methods: Appendix 1, Appendix 1
• FPGA: Section 1: Chapter 1
  • design and test: Section 1: Chapter 1
  • field-programmable versus mask-programmable tasks: Section 1: Chapter 1
• Full-scan: Appendix 1
• Functional test: Section 2: Chapter 5

G

• Gate array: Section 2: Chapter 3, Section 2: Chapter 3, Section 4: Chapter 4
  • definition: Section 1: Chapter 1
  • gate count: Section 3: Chapter 2
• Gate oxide short: Section 4: Chapter 1
• Glassivation: Section 4: Chapter 1, Section 4: Chapter 1
• Government qualification programs: Appendix 2. See also Vendor evaluation: evaluating government qualification programs
  • the future: Appendix 2
• Government standards: Section 2: Chapter 2

H

• Hard macro: Section 2: Chapter 4, Section 2: Chapter 4
• Hardness of commercial processes: Section 2: Chapter 4
• HDLs: Section 1: Chapter 4, Section 3: Chapter 2, Appendix 1
  • and synthesis: Appendix 1
  • behavioral models: Appendix 1
  • logic models: Appendix 1
  • register-transfer models: Appendix 1
  • Verilog: Section 1: Chapter 4
  • VHDL: Section 1: Chapter 4, Appendix 1
• Hot carrier: Section 4: Chapter 3
• Hot chuck: Section 4: Chapter 1
• Hybrid: Section 4: Chapter 1

I

• I/O: Section 3: Chapter 2, Section 3: Chapter 2
• IDD current limiting: Section 3: Chapter 4
• I_DDQ testing: Section 2: Chapter 5, Section 3: Chapter 2, Section 4: Chapter 1, Section 4: Chapter 4
• IEEE standard 1149.1: Section 3: Chapter 3, Section 3: Chapter 3, Appendix 1
• Implementation: Section 3: Chapter 2
  • ASIC family capabilities: Section 3: Chapter 2
  • review. See Review process: implementation review
  • system-level: Section 3: Chapter 2
• In-line tests: Section 4: Chapter 4
• In-process monitoring: Appendix 2
• Infant mortality: Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Appendix 7
• Information management: Section 1: Chapter 4
• Interconnections: Section 3: Chapter 2, Section 3: Chapter 2
• Interface traps: Section 3: Chapter 2
• Ionizing radiation: Section 3: Chapter 2

J

• JEDEC: Section 4: Chapter 4
• Joint-Army-Navy (JAN): Appendix 2
• JTAG: Appendix 1, Appendix 1

L

• Latch-up: Section 4: Chapter 2
• Latent defect: Section 4: Chapter 1
• Layout
  • physical. See ASIC: system partitioning
• Layout tools: Section 2: Chapter 5
  • back annotation tools: Section 2: Chapter 5
  • design rule check (DRC) tools: Section 2: Chapter 5
  • electrical rule check (ERC) tools: Section 2: Chapter 5
  • layout verification tools: Section 2: Chapter 5
  • parameter extraction tools: Section 2: Chapter 5
  • transistor layout and auto-router tools: Section 2: Chapter 5
• Leakage current: Section 4: Chapter 2
• Level sensitive scan design (LSSD): Section 3: Chapter 3
• Life test: Section 4: Chapter 2, Section 4: Chapter 3, Section 4: Chapter 3
• Linear feedback shift register (LFSR): Section 3: Chapter 3
• Linear-energy transfer LET: Section 3: Chapter 4
• Logic partitioning. See Partitioning
• Lot tolerance percent defective (LTPD): Section 4: Chapter 3, Appendix 4

M

• Marking Diagram: Appendix 6
• Mask: Section 4: Chapter 4
• Metal stress voiding: Section 4: Chapter 1
• Metallization: Section 4: Chapter 1, Section 4: Chapter 4
• MIL-H-38534: Section 4: Chapter 1
• MIL-HDBK-217: Appendix 7, Appendix 7
  • benefits: Appendix 7
  • limitations: Appendix 7
• MIL-I-38535: Section 4: Chapter 1, Section 4: Chapter 3, Section 4: Chapter 3, Appendix 2, Appendix 2, Appendix 3
• MIL-M-38510: Appendix 2, Appendix 3
  • MIL-M-38510/605-608: Appendix 2
• MIL-S-19500: Appendix 2
• MIL-STD-750: Appendix 2
• MIL-STD-883: Section 2: Chapter 2, Section 4: Chapter 1, Section 4: Chapter 3, Section 4: Chapter 3, Appendix 1, Appendix 2, Appendix 3
• MIL-STD-976: Appendix 2
• MIL-STD-977: Section 4: Chapter 1
• Modeling: Section 4: Chapter 2
  • and the design cycle: Appendix 1
  • and translation
    • perspective: Appendix 1
  • ASIC program: Appendix 1
  • fabrication process: Appendix 1
  • logic model: Section 3: Chapter 2
  • model compiler: Appendix 1
  • model development: Appendix 1
  • model verification: Section 2: Chapter 4
  • parameter modeling: Section 3: Chapter 2
  • switch-level: Appendix 1
• Multi-chip devices: Section 4: Chapter 1
• Multiple-bit upset: Section 3: Chapter 4

N

• Netlist: Section 3: Introduction
  • generation: Section 3: Chapter 2
• Non-destructive bond pull test: Section 4: Chapter 3

O

• Observability: Section 3: Chapter 2, Section 3: Chapter 3, Section 3: Chapter 3
• Off-the-shelf: Section 4: Chapter 4
  • component board design: Section 3: Inroduction
• Open interconnect: Section 4: Chapter 1, Section 4: Chapter 1
• Oxide layer: Section 4: Chapter 1
• Oxide thickness: Section 3: Chapter 4

P

• Packaging: Section 1: Chapter 3, Section 3: Chapter 2, Section 3: Chapter 2, Section 4: Chapter 1. See also Vendor evaluation: evaluating packaging
  • package outline Appendix 6
• Parametric monitor (PM): Appendix 2
• Parasitic bipolar transistor: Section 3: Chapter 4
• Part acceptance: Section 1: Chapter 1, Section 1: Chapter 2, Section 4: Chapter 4
  • approach: Section 4: Chapter 1
  • as it relates to quality and reliability: Section 4: Introduction
  • bare die: Section 4: Chapter 1
  • contracting for: Section 4: Chapter 1
  • designer-developed tests in: Section 4: Chapter 1
  • how part acceptance information is distributed in: Section 4: Introduction
  • in government qualification programs: Section 4: Introduction
  • in process and design qualification: Section 4: Introduction
  • perspective on: Section 4: Chapter 4
• Part count method: Appendix 7
• Part stress analysis method: Appendix 7
• Partitioning: Section 3: Chapter 2, Section 3: Chapter 2, Section 3: Chapter2
  • cross-sectional: Section 3: Chapter 2
  • distributive: Section 3: Chapter 2
  • functional: Section 3: Chapter 2
  • system. See ASIC: system partitioning
• PDA: Section 4: Chapter 3, Section 4: Chapter 3, Appendix 4
• Percent defective allowable. See PDA
• Performance: Section 3: Chapter 2
• Physical layout: Section 1: Chapter1
• Pin Assignment: Appendix 6
• Place and route: Appendix 1
• Planning
  • equipment and tool. See ASIC: equipment and tool planning; ASIC: program: resources
  • personnel: Section 1: Chapter 2
• Post-layout
  • analysis: Appendix 1
  • performance: Section 3: Chapter 2
• Power cycling: Section 3: Chapter 4
• Power dissipation: Section 3: Chapter 2
• Preliminary design review (PDR). See review process: preliminary design review
• Process: Section 4: Chapter 3, Section 4: Chapter 3
  • scaling: Appendix 1
• Process (or device) learning factor: Appendix 7
• Process control: Section 4: Chapter 3. See also Statistical process control
• Process maturity: Section 2: Chapter 3
• Process monitor: Section 4: Chapter 1
• Process technology: Section 2: Chapter 3
• Process variation: Section 4: Chapter 2
• Procurement:
  • designer support of: Section 3: Introduction
  • in ASIC design: Appendix 5
  • in ASIC management: Appendix 5
    • ASIC tasks and responsibilities: Appendix 5
    • information management: Appendix 5
    • resource planning: Appendix 5
    • review process: Appendix 5
    • risk assessment and contingency planning: Appendix 5
  • in part acceptance: Appendix 5
  • in vendor evaluation: Appendix 5
    • management evaluation: Appendix 5
    • technical evaluation: Appendix 5
  • support: Appendix 5
• Program budgeting. See ASIC: program: budgeting
• Proof-of-design parts: Section 4: Chapter 1
• Propagation delay: Section 4: Chapter 1
• Prototype: Section 4: Chapter 1, Section 4: Chapter 2
• Punchthrough: Section 4: Chapter 1

Q

• QCI: Section 4: Chapter 2, Section 4: Chapter 2, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3
  • repeated tests: Section 4: Chapter 3
  • sampling intervals: Section 4: Chapter 3
  • specification of: Section 4: Chapter 3
  • types of tests in: Section 4: Chapter 3
  • use of QCI samples for flight application: Section 4: Chapter 3
• QML: Section 2: Chapter 2, Section 4: Introduction, Section 4: Chapter 1, Section 4: Chapter 1, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 4, Appendix 1, Appendix 4. See also Government qualification programs; Screening: QML and QPL methods
  • a brief comparison with QPL: Appendix 2
  • certification: Appendix 2
  • history and approach: Appendix 2
  • limitations: Appendix 2
  • qualification: Appendix 2
  • steps toward producing a QML-qualified ASIC: Appendix 2
  • third party involvement: Appendix 2
• QMP. See Quality Management Plan
• QPL: Section 2: Chapter 2, Section 4: Introduction, Section 4: Chapter 1, Section 4: Chapter 1, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 4, Appendix 1, Appendix 4. See also Government qualification programs; Screening: QML and QPL methods
  • a brief comparison with QML: Appendix 2
  • approach to qualification: Appendix 2
  • certification: Appendix 2
  • gate array program: Appendix 2
  • history and approach: Appendix 2
  • qualification: Appendix 2
• Qualified Manufacturers Listing. See QML
• Qualified Parts Listing. See QPL
• Quality: Section 4: Introduction
• Quality assurance: Section 4: Introduction
• Quality conformance inspection. See QCI
• Quality factor: Appendix 7
• Quality Management Plan (QMP): Section 2: Chapter 2, Appendix 2
• Quiescent current: Section 3: Chapter 2, Section 4: Chapter 1

R

• Rad: Section 3: Chapter 4
• Radiation
  • annealing: Appendix 3
  • atomic displacement: Appendix 3
  • cosmic rays: Appendix 3
  • displacement damage: Appendix 3
  • effects on semiconductor devices: Appendix 3
  • environment in space: Appendix 3
  • fault tolerance: Appendix 3
  • hard-errors: Appendix 3
  • hardening: Section 2: Chapter 3, Section 3: Chapter 2, Section 4: Chapter 3, Appendix 3, Appendix 3
  • initial recombination: Appendix 3
  • interface traps: Appendix 3
  • ionization: Appendix 3
  • nuclear interactions: Appendix 3
  • physics of radiation interactions with solids: Appendix 3
  • radiation trapped by planetary magnetic fields: Appendix 3
  • rebound effect: Appendix 3
  • Rutherford scattering: Appendix 3
  • shielding: Appendix 3
  • single-event effect. See SEE
  • solar flares: Appendix 3
  • South Atlantic Anomaly (SAA): Appendix 3
  • space radiation environment
    • design for: Section 3: Introduction
    • effects on integrated circuits: Appendix 3
    • strategies for withstanding: Appendix 3
  • tolerance: Section 2: Chapter 3, Section 2: Chapter 4
  • total ionizing dose. See TID
  • trapped holes: Appendix 3
  • Van Allen belts: Appendix 3
• Radiation hardening: Section 3: Chapter 4, Section 3: Chapter 4
• Radiation-aware design tools: Section 3: Chapter 4
• Radiation-hardened cells: Section 3: Chapter 4
• Radiation-hardened process: Section 3: Chapter 4
• Random-access scan: Section 3: Chapter 3
• Redundancy: Section 3: Chapter 2
• Reliability: Section 4: Introduction, Section 4: Chapter 3, Section 4: Chapter 4, Appendix 7
  • basic calculations: Appendix 7
    • Arrhenius model: Appendix 7
    • constant failure rate model: Appendix 7
    • cumulative distribution function: Appendix 7
    • example: Appendix 7
    • failure time distributions: Appendix 7
    • hazard rate: Appendix 7
    • mean time to failure: Appendix 7
    • probability density function: Appendix 7
    • survivor function: Appendix 7
  • basic concepts: Appendix 7
  • defect-driven: Appendix 7
  • modeling: Appendix 7
• Requirements
  • identifiying: Section 1: Chapter 4
  • setting. See ASIC: setting requirements
• Resource planning. See ASIC: resource planning
• Reverse-bias pn junction: Section 4: Chapter 1
• Review process: Section 1: Chapter 5
  • activities: Section 1: Chapter 5
  • chip sign-off review: Section 1: Chapter 1
  • critical design review (CDR): Section 1: Chapter 1, Section 1: Chapter 5
  • documentation: Section 1: Chapter 5
  • flight build review: Section 1: Chapter 1, Section 1: Chapter 5
  • implementation review: Section 1: Chapter 5
  • major reviews and their deliverables: Section 1: Chapter 5
  • nature of: Section 1: Chapter 5
  • preliminary design review (PDR): Section 1: Chapter 1, Section 1: Chapter 5
  • review meeting: Section 1: Chapter 5
  • schematic review: Section 1: Chapter 1
  • selecting personnel: Section 1: Chapter 5
  • specifications review: Section 1: Chapter 1, Section 1: Chapter 5
• Risk assessment: Section 1: Chapter 3
• Risk management
  • a practical guide: Section 1: Chapter 3
  • and contingency planning: Section 1: Chapter 3
• Rome Laboratories: Section4: Chapter 4

S

• Sacrificial package test: Section 4: Chapter 1
• Scan design: Section 3: Chapter 2, Section 3: Chapter 3
• Scan path: Section 3: Chapter 3
• Scan/set logic: Section 3: Chapter 3
• Scanning electron microscope: Section 4: Chapter 1
• Schematic capture: Section 3: Chapter 2
  • logic-level: Section 3: Chapter 2
• Schematic correlation: Section 3: Chapter 2
• Screening: Section 4: Introduction, Section 4: Chapter 1, Section 4: Chapter 2, Section 4: Chapter 2, Section 4: Chapter 3, Section 4: Chapter 3, Section 4: Chapter 3
  • QML and QPL methods: Section 4: Chapter 3
  • specification of: Section 4: Chapter 1
• SEC. See Standard evaluation circuit
• SEE: Section 4: Chapter 2, Appendix 3
  • burnout: Appendix 3
  • funneling: Appendix 3
  • latch-up: Appendix 3
  • linear energy transfer (LET): Appendix 3
  • snapback: Appendix 3
  • soft errors: Appendix 3
• Shift register: Section 3: Chapter 2, Section 3: Chapter 2, Section 3: Chapter 2
  • latch (SRL): Section 3: Chapter 3
• SHMOO plots: Section 4: Chapter 2
• Signature analysis: Section 3: Chapter 3
• Silicon on insulator (SOI): Section 3: Chapter 4, Section 3: Chapter 4
• Silicon-on-sapphire (SOS): Section 3: Chapter 4
• Simulation: Section 3: Chapter 2 , Appendix 1
  • circuit and timing: Section 3: Chapter 2
  • formal methods vs simulation: Appendix 1
  • functional: Section 3: Chapter 2
  • numerical analysis: Section 3: Chapter 2
  • timing analysis: Section 3: Chapter 2
    • dithering: Section 3: Chapter 2
    • static: Section 3: Chapter 2
• Simulation/verification tools
  • circuit simulation tools: Section 2: Chapter 5
  • fault simulation: Section 2: Chapter 5
  • logic simulation: Section 2: Chapter 5
  • simulation compare: Section 2: Chapter 5
  • switch level simulation: Section 2: Chapter 5
• Simulator: Section 4: Chapter 2, Appendix 1
• Single-Event Effects (SEE): Section 3: Chapter 4
• Single-event transients: Section 3: Chapter 4:
• Single-event upset: Section 3: Chapter 4
• Slash sheet: Section 4: Chapter 3, Appendix 2, Appendix 2
• Snapback: Section 3: Chapter 4
• Soft macro: Section 2: Chapter 4
• SPC. See Statistical process control
• Specification: Section 1: Chapter 4, Section 3: Chapter 1, Section 4: Chapter 1, Section 4: Chapter 1, Section 4: Chapter 3
  • creating and documenting different levels of: Section 1: Chapter 4
  • general specification: Section 4: Chapter 1, Section 4: Chapter 3
  • screening: Section 4: Chapter 3, Section 4: Chapter 3
  • statement of work (SOW): Section 4: Chapter 1
  • testability constructs: Appendix 6
• Specification, technical
  • additional requirements: Section 3: Chapter 1
  • applicable documents: Section 3: Chapter 1, Appendix 6
  • ASIC signal designations and description: Section 3: Chapter 1
  • case study: Appendix 6
  • chip overview: Section 3: Chapter 1, Appendix 6
  • conventions: Section 3: Chapter 1, Appendix 6
  • electrical characteristics: Section 3: Chapter 1, Appendix 6
    • absolute maximum rating: Section 3: Chapter 1
    • ac characteristics: Section 3: Chapter 1
    • burn-in: Section 3: Chapter 1, Appendix 6
    • dc characteristics: Section 3: Chapter 1
    • delta limits: Section 3: Chapter 1, Appendix 6
    • electrical test requirements: Section 3: Chapter 1
    • I_DDQ Testing: Appendix 6
    • I_DDQ testing: Section 3: Chapter 1
    • pull-up and pull down resistors: Section 3: Chapter 1
    • recommended operating conditions: Section 3: Chapter 1
  • functional description: Section 3: Chapter 1, Appendix 6
  • physical characteristics: Section 3: Chapter 1, Appendix 6
    • bonding diagram: Section 3: Chapter 1
    • device statistics: Section 3: Chapter 1
    • exceptions to any procurement document: Section 3: Chapter 1
    • marking diagram: Section 3: Chapter 1
    • package outline: Section 3: Chapter 1
    • pin assignment: Section 3: Chapter 1
  • scope: Section 3: Chapter 1
  • switching test circuit and waveforms: Appendix 6
  • testability constructs: Section 3: Chapter 1
  • timing analysis: Appendix 6
  • timing diagrams: Appendix 6
• SPICE: Appendix 1
• Standard cell: Section 2: Chapter 3 Section 3: Chapter 2
  • definition: Section 1: Chapter 1
• Standard evaluation circuit (SEC): Appendix 2
• Standardized military drawing (SMD): Appendix 2
• Standby current: Sectin 4: Chapter 2
• State capture, multiple device: Section 3: Chapter 2
• Statistical process control: (SPC): Section 4: Chapter 3, Appendix 2
• Step coverage: Section 4: Chapter 1
• Structural test: Section 2: Chapter 5
• Stuck-at fault: Section 3: Chapter 2, Section 3: chapter 3, Section 4: Chapter 1, Section 4: chapter 1, Section 4: Chapter 4
• Subsystem characterization. See Characterization: system
• Support groups
  • external: Section 1: Chapter 2
• Surface-mount technology: Section 3: Chapter 3
• Synthesis: Appendix 1. See HDLs: and synthesis
  • reverse synthesis: Appendix 1
• System
  • partitioning. See ASIC: system partitioning
  • sequential logic: Section 3: Chapter 3
  • verification: Section 3: Chapter 2

T

• Tasks
  • design and test: Section 1: Chapter 2
  • failure analysis: Section 1: Chapter 2
• TCI: Section 4: Chapter 3, Section 4: Chapter 3
• Technical evaluation: Section 2: Introduction
• Technology characterization vehicle (TCV): Appendix 2
• Technology conformance inspection. See TCI
• Technology review board (TRB): Section 4: Chapter 3, Appendix 2
• Temperature acceleration factor: Appendix 7
• Temperature cycling: Section 4: Chapter 2, Section 4: Chapter 3
• Test: Section 3: Chapter 2, Section 3: Chapter 2, Section 4: Chapter 1
  • access port (TAP): Section 3: Chapter 3
  • and characterization: Section 1: Chapter 1
  • at-speed functional: Section 4: Chapter 1, Section 4: Chapter 1. See also Fault models: at-speed functional
  • data standards: Section 3: Chapter 3
  • designer support of: Section 4: Chapter 1
  • die holder tests: Section 4: Chapter 1
  • fault detection and localization (FDL), IEEE PAR f: Section 3: Chapter 3
  • generation: Section 3: Chapter 2
    • at-speed functional: Section 3: Chapter 2
    • quiescent current: Section 3: Chapter 2
  • generation tools: Section 2: Chapter 5
  • I/O: Section 3: Chapter 3
  • I_DDQ: Section 4: Chapter 1. See also I_DDQ testing
  • internal: Section 3: Chapter 3
  • need for more than one type of: Section 4: Chapter 1
  • requirements and specification language (TRSL): Section 3: Chapter 3
  • structure: Section 4: Introduction, Section 4: Chapter 1, Section 4: Chapter 3, Section 4: Chapter 3
    • for detecting defects: Section 4: Chapter 1
  • stuck at fault. See Stuck at fault
  • testability: Section 2: Chapter 3, Section 2: Chapter 4
  • tester limitations: Section 4: Chapter 1
  • to failure: Section 4: Chapter 2
  • transient ionizing irradiation: Section 4: Chapter 3
  • vectors: Section 3: Chapter 2, Section 4: Chapter 1, Section 4: Chapter 1, Section 4: Chapter 2, Section 4: Chapter 3, Section 4: Chapter 3
    • AC parametric vectors: Section 4: Chapter 1
    • DC parametric vectors: Section 4: Chapter 1
    • functional vectors: Section 4: Chapter 1
    • specification of: Section 4: Chapter 1
    • structural vectors: Section 4: Chapter 1
    • WAVES test vector standard: Section 3: Chapter 3, Appendix 1
• TID: Section 4: Chapter 2, Section 4: Chapter 3, Appendix 3
• Time to market: Section 3: Chapter 2
• Time-dependent dielectric breakdown (TDDB): Section 4: Chapter 1, Sectin 4: Chapter 3
• Timing
  • margin analysis: Section 3: Chapter 2
  • margins: Section 3: Chapter 2
  • setup and hold: Section 3: Chapter 2
  • verification: Section 3: Chapter 2
• Toggle coverage: Section 3: Chapter 2
• Tools: Section 1: Chapter 2, Section 2: Chapter 2, Section 4: Chapter 4
  • development of: Appendix 1, Appendix 1
  • evaluation issues: Appendix 1
  • layout tools: Appendix 1
  • "open framework" tool design: Appendix 1
• Total Ionizing Dose (TID): Section 3: Chapter 4
• Total Quality Management (TQM): Appendix 2
• Transient analyses: Appendix 1
• Transient phenomena: Section 3: Chapter 4
• Transistor-transistor logic: Section 3: Chapter 2
• Translation: Appendix 1, Appendix 1. See also Modeling: and translation
  • ASIC level to system level: Appendix 1
  • design implementation translation matrix: Appendix 1
  • design language standards: Appendix 1
  • planning for: Appendix 1
  • system level to ASIC level: Appendix 1
  • to tester: Appendix 1
• Translators: Appendix 1
• TRSL. See Test: requirements and specification language
• Tunneling: Section 4: Chapter 1

V

• Vacuum chuck: Section 4: Chapter 1
• Vendor evaluation: Section 1: Chapter 2
  • ASIC development tools analysis: Section 2: Chapter 5
  • design library analysis: Section 2: Chapter 4
  • evaluating ASIC design trade-offs: Section 2: Chapter 3
  • evaluating ASIC technology: Section 2: Chapter 3
  • evaluating government qualification programs: Section 2: Chapter 2,
  • evaluating packaging: Section 2: Chapter 3
  • evaluating quality design methodology: Section 2: Chapter 2
  • evaluating team activity: Section 2: Chapter 2
  • information management capabilities analysis: Section 2: Chapter 5
  • management evaluation: Section 2: Chapter 1
    • business plan review: Section 2: Chapter 1
    • marketing strategy and procurement support review: Section 2: Chapter 1
    • past performance analysis: Section 2: Chapter 1
    • personnel, facilities, and equipment analysis: Section 2: Chapter 1
    • schedule and cost review: Section 2: Chapter 1
    • top level organization review: Section 2: Chapter 1
  • modeling and translation issues: Appendix 1
  • overall flow: Section 2: Introduction
  • process technology analysis: Section 2: Chapter 3
  • schedule: Section 1: Chapter 2
  • vendor tool support and training: Section 2: Chapter 5
• Vendor management: Section 2: Chapter 1
• Vendor selection: Section 1: Chapter 1
• Visual inspection: Section 4: Chapter 1
• Voltage stress factor: Appendix 7

W

• Wafer acceptance
  • how QML and QPL differ in: Section 4: Chapter 1
• Wafer lot : Section 4: Chapter 1
• WAVES. See Test: vectors: WAVES test vector standard

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